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HRA

Robot
Herní styl Miscellaneous
Multiplayer Bez multiplayeru
Rok vydání 2000
Programátor Richard Bayliss
Grafik (Unknown)

INTRO

WORKSHOP - Projects - SIMM in C64

SIMM to Commodore 64

This is a copy, the original article can be found here:
http://members.elysium.pl/ytm/html/simm.html

After upgrading memory in my 386 from 5MB to 8MB four 256kB SIMMs left me. I started searching for a project that would interface SIMM to C64/128 somehow but I didn't found anything like that. Having some spare time I simply removed memory chips from one of my C64 computers and interfaced a 256kB SIMM instead. Suprisingly - it works.
Note: thank to Gianluca 'Hiryu' Agnocchetti there is also an Italian translation of this article. It has better pictures :).

Interface

It is nothing special. You simply must desolder memory chips from your C64 and wire SIMM to the contacts that will be available. I used 21 wires to connect these signals:

GND, VCC, /CAS, /RAS, /WE, A0-A7, D0-D7.

one to one to their counterparts on the C64 board. On the SIMM I also connected A8 line to GND because I don't want to mess with it right now. Pinouts are below. Note that e.g. D1 from RAM does not have to be connected to D1 on SIMM. It is only required that D0-D7 from board are connected to D0-D7 on SIMM, order is not important. The same is for address lines, but except A8 on SIMM.

Here are pictures of the test C64, they are not very descriptive but give the evidence and general impression. Click to enlarge.

Future

There are two problems to be solved: memory refresh and using whole memory space. It seems for me that memory refresh is not an issue in case of 256kB SIMM because from Marko Makela's document about expanding C128 memory to 256/512/1024kB I know that 256kb DRAMs don't need A8 for refresh. More advanced techiques (like CAS-before-RAS refresh) would be required for larger SIMMs. The second issue - actually using this memory needs a smart design that will allow to use the extra RAM in the standard way of C64/128 - as memory banks with some space shared among the banks. I think that the best way would be not to invent something new, but to be compatible with +60k expansion and +256k by Soci/Singular. I don't have any ideas right know how it can be done, but I think I will make something :)

Update

According to mail archives of cbm-hackers list and some discussion with Nick Coplin it seems that doing simple interface for full 256kB SIMMs is not possible. External memory refresh generator is required due to fact that SIMMs need 9 bit counter and VIC can provide only 8 bits (which is quite nice because C64/128 chips need only 7 bit counter). SIMMs with larger capacity will require even more bits for counter.

Pinouts

4464 (or similar) 64kx4 DRAM. Your C64 has two of them.

     +----------+
 /OE |1  +--+ 18| GND
  D0 |2       17| D3
  D1 |3       16| /CAS
 /WE |4       15| D2
/RAS |5  4464 14| A0
  A6 |6       13| A1
  A5 |7       12| A2
  A4 |8       11| A3
 VCC |9       10| A7
     +----------+

4164 64kx1 DRAM. Your C64 has eight of them.

     +--------+
  NC | 1 \/ 16| GND
   D | 2    15| /CAS
 /WE | 3    14| Q
/RAS | 4    13| A6
  A0 | 5    12| A3
  A2 | 6    11| A4
  A1 | 7    10| A5
 VCC | 8     9| A7
     +--------+

30 PIN SIMM (At the computer)

30 PIN SIMM at the computer.

Pin Name Description
1 VCC +5 VDC
2 /CAS Column Address Strobe
3 DQ0 Data 0
4 A0 Address 0
5 A1 Address 1
6 DQ1 Data 1
7 A2 Address 2
8 A3 Address 3
9 GND Ground
10 DQ2 Data 2
11 A4 Address 4
12 A5 Address 5
13 DQ3 Data 3
14 A6 Address 6
15 A7 Address 7
16 DQ4 Data 4
17 A8 Address 8
18 A9 Address 9
19 A10 Address 10
20 DQ5 Data 5
21 /WE Write Enable
22 GND Ground
23 DQ6 Data 6
24 A11 Address 11
25 DQ7 Data 7
26 QP Data Parity Out
27 /RAS Row Address Strobe
28 /CASP Something Parity ????
29 DP Data Parity In
30 VCC +5 VDC

Note: SIMM above is a 4MBx9.
QP & DP is N/C on SIMMs without parity.
A9 is N/C on 256kB.
A10 is N/C on 256kB & 1MB. A11 is N/C on 256kB, 1MB & 4MB.

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